BlitzCast™ — Ultra-low Latency H.265 Semiconductor IP
BlitzCast™ delivers 2ms codec latency and true sub-frame performance across custom ASIC and FPGA implementations—empowering hardware engineers to build mission-critical, real-time video streaming systems without compromise.
Technical Specifications
Performance Specifications Matrix
Validated latency, resolution, and bandwidth figures for the BlitzCast™ H.265 encoder and decoder IP.
| Codec Engine Latency | 2 milliseconds (encoding + decoding combined) |
|---|---|
| End-to-End Latency (1Gbps LAN) | Sub-frame latency |
| End-to-End Latency (WiFi) | ~1 frame (~16.7ms @ 4K/60fps or ~7ms @ 4K/144fps) with Tx & Rx using BlitzCast™ |
| End-to-End Latency of AirPlay- or Miracast-like Applications (WiFi) | <50ms (Standard 3rd party H.265 host encoder to BlitzCast™ decoder) |
| Supported Resolutions | 4K60 (4:4:4, 10-bit), 4K144 (4:2:0, 8-bit), 8K60 (4:2:0, 8-bit) |
| Bandwidth / Bitrate | Configurable from 2 Mbps to 150 Mbps for 4K60 streams |
Implementation & PPA
FPGA vs. ASIC Implementation
BlitzCast™ is architected for maximum flexibility. Whether developing low-volume, high-margin defense technology requiring an FPGA video codec IP, or scaling mass-market consumer electronics via ASIC, our core is highly optimized for power, performance, and area.
ASIC Node Benchmark
Optimized for mass-market silicon with an exceptionally lean logic footprint and minimal power draw.
- Gate Count
- ~3M
- gates
- Power Consumption
- ~0.5W
- ultra-low power
FPGA Resource Utilization
Highly optimized logic footprint that leaves ample room for custom system-on-chip logic alongside the codec.
- Logic
- ~150K
- LUTs
- Block RAM
- ~50
- BRAM (36 Kb each)
Architectural Overview
The 2ms Latency Breakthrough
The Bottleneck of Conventional Architectures
Traditional inter-prediction requires full-frame buffering before processing can begin. At 60fps that introduces a 16.7ms frame delay, and the decoder's picture buffer (DPB) adds another frame—yielding a 33.4ms baseline. In real-world glass-to-glass deployments, network and pipeline overhead balloon this to 100ms+.
Fractional-Frame Processing
BlitzCast™ re-engineers the data path around a fractional 64-line buffer—the absolute minimum required by advanced HEVC algorithms. By processing slices as they arrive rather than waiting for full frames, BlitzCast™ achieves 2ms codec latency and below 17ms glass-to-glass latency at 4K60.
Under The Hood
How We Sustain Real-Time Processing
On-Chip SRAM vs. External DDR
Utilizes localized on-chip memory instead of DDR to eliminate access latency and reduce per-bit energy by 10x to 100x.
Systolic Motion Estimation
A highly over-designed hardware accelerator featuring systolic motion estimation to eliminate pipeline stalls under limited buffering constraints.
Micro-Threaded Multi-Processor
Custom multi-processor scheduling hardware threads with zero overhead to maximize utilization and ensure uninterrupted real-time video streaming.
FAQ
Technical & Silicon Integration FAQ
What are the SWaP (Size, Weight, and Power) specifications for BlitzCast™?
BlitzCast™ is engineered specifically for SWaP-constrained embedded platforms and custom SoCs:
- Gate Count: Approximately 3 Million Logic Gates on a standard 22nm process node.
- Power Consumption: Operating power as low as ~0.5W under typical 4K60 processing workloads.
- Footprint: Minimal internal SRAM footprint, maximizing cost-efficiency for ASIC tape-outs and mid-tier FPGAs.
How does BlitzCast™ optimize memory bandwidth and reduce DRAM bus load?
Standard video codecs saturate host DDR memory by continuously writing and reading full reference frames. BlitzCast™ incorporates an advanced line-buffer memory controller combined with optimized intra-refresh reference patterns. This drastically minimizes external DRAM access, prevents system-on-chip (SoC) memory bus contention, and avoids packet starvation under bursty traffic conditions.
Which FPGA architectures and foundry nodes are pre-validated for BlitzCast™?
- AMD / Xilinx: Pre-validated on Kintex-7, Zynq UltraScale+ and Kintex UltraScale+.
- ASIC Foundry Readiness: RTL and synthesized flows compatible with major foundries (TSMC, GlobalFoundries, SMIC).
What maximum video resolutions, frame rates, and color formats are supported?
BlitzCast™ scales across mission-critical video pipelines:
- Resolutions & Rates: Up to 8K at 60fps, 4K at 144fps, and high-framerate 1080p pipelines.
- Chroma & Bit Depth: Supports 4:2:0, 4:2:2, and 4:4:4 chroma sampling at up to 10-bit color for visually lossless fidelity.
- Bitrate Range: Configurable output throughput from 2 Mbps (narrowband wireless) up to 150 Mbps (high-tier 4K60 ProAV).
Get Started
Benchmark BlitzCast™ on Your Platform
Request the full technical datasheet and an evaluation kit to benchmark 2ms latency H.265 encoding and decoding on your target ASIC or FPGA platform. Our IP licensing team is ready to support your design.